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STK10C48
2K x 8 nvSRAM QuantumTrapTM CMOS Nonvolatile Static RAM
FEATURES
* 20ns, 25ns, 35ns and 45ns Access Times * STORE to EEPROM Initiated by Hardware * RECALL to SRAM Initiated by Hardware or Power Restore * Automatic STORE Timing * 10mA Typical ICC at 200ns Cycle Time * Unlimited READ, WRITE and RECALL Cycles * 1,000,000 STORE Cycles to EEPROM * 100-Year Data Retention over Full Industrial Temperature Range * Commercial and Industrial Temperatures * 28-Pin 300 mil PDIP, 300 mil SOIC and 350 mil SOIC Packages
DESCRIPTION
The Simtek STK10C48 is a fast static RAM with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data may easily be transferred from the SRAM to the EEPROM (the STORE operation), or from the EEPROM to the SRAM (the RECALL operation), using the NE pin. Transfers from the EEPROM to the SRAM (the RECALL operation) also take place automatically on restoration of power. The STK10C48 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. The STK10C48 features industry-standard pinout for nonvolatile RAMs.
BLOCK DIAGRAM
EEPROM ARRAY 32 x 512 ROW DECODER
PIN CONFIGURATIONS
NE NC A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
A5 A6 A7 A8 A9
STORE STATIC RAM ARRAY 32 x 512 RECALL
VCC W NC A8 A9 NC G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
28 - 300 PDIP 28 - 300 SOIC 28 - 350 SOIC
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
INPUT BUFFERS
COLUMN I/O COLUMN DEC
PIN NAMES
STORE/ RECALL CONTROL
A0 - A10 W DQ0 - DQ7 Address Inputs Write Enable Data In/Out Chip Enable Output Enable Nonvolatile Enable Power (+ 5V) Ground
A0 A1 A2 A3 A4 A10
E
G NE E W
G NE VCC VSS
July 1999
3-1
STK10C48
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to VSS . . . . . . . . . . -0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS
COMMERCIAL SYMBOL ICC
c
(VCC = 5.0V 10%)b
INDUSTRIAL UNITS MIN MAX 95 85 75 65 3 10 30 25 21 18 750 1 5 2.2 VSS - .5 2.4 0.4 0 70 -40 VCC + .5 0.8 2.2 VSS - .5 2.4 0.4 85 MIN MAX N/A 90 75 65 3 10 N/A 26 22 19 750 1 5 VCC + .5 0.8 mA mA mA mA mA mA mA mA mA mA A A A V V V V C tAVAV = 20ns tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns All Inputs Don't Care, VCC = max W (V CC - 0.2V) All Others Cycling, CMOS Levels tAVAV = 20ns, E VIH tAVAV = 25ns, E VIH tAVAV = 35ns, E VIH tAVAV = 45ns, E VIH E (V CC - 0.2V) All Others VIN 0.2V or (VCC - 0.2V) VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All Inputs All Inputs IOUT = - 4mA IOUT = 8mA NOTES
PARAMETER Average VCC Current
1
ICC ICC ISB
d
2
c
Average VCC Current during STORE Average VCC Current at tAVAV = 200ns 5V, 25C, Typical Average VCC Current (Standby, Cycling TTL Input Levels)
3
e
1
ISB
e
2
VCC Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current Off-State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature
IILK IOLK VIH VIL VOH VOL TA
Note b: Note c: Note d: Note e:
The STK10C48-20 requires VCC = 5.0V 5% supply to operate at specified speed. ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 1 3 ICC is the average current required for the duration of the STORE cycle (tSTORE ) . 2 E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
480 Ohms OUTPUT 255 Ohms
CAPACITANCEf
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance
(TA = 25C, f = 1.0MHz)
MAX 8 7 UNITS pF pF CONDITIONS
V = 0 to 3V V = 0 to 3V
30 pF INCLUDING SCOPE AND FIXTURE
Note f:
These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
July 1999
3-2
STK10C48
SRAM READ CYCLES #1 & #2
SYMBOLS NO. 1 2 3 4 5 6 7 8 9 10 11 PARAMETER #1, #2 tELQV tAVAVg tAVQV
h
(VCC = 5.0V 10%)b
STK10C48-20 STK10C48-25 MIN MAX 25 25 22 8 5 5 7 0 7 0 25 0 25 0 10 0 35 5 5 10 0 13 0 45 25 10 5 5 13 0 15 35 35 15 5 5 15 STK10C48-35 MIN MAX 35 45 45 20 STK10C48-45 UNITS MIN MAX 20 20 MIN MAX 45 ns ns ns ns ns ns ns ns ns ns ns
Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby
tGLQV tAXQXh tELQX tEHQZi tGLQX tGHQZi tELICCHf tEHICCL
e, f
Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle. Note h: I/O state assumes E, G < VIL, W > VIH , and NE VIH; device is continuously selected. Note i: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
tAVAV ADDRESS
5 3 2
tAVQV DATA VALID
tAXQX DQ (DATA OUT)
SRAM READ CYCLE #2: E Controlledg
tAVAV ADDRESS tELQV E
6 tELQX 1 2
tEHICCL
7
1 1
tEHQZ
G tGLQV
4
tGHQZ
9
tGLQX DQ (DATA OUT)
10 tELICCH DATA VALID
8
ACTIVE
ICC
STANDBY
July 1999
3-3
STK10C48
SRAM WRITE CYCLES #1 & #2
SYMBOLS NO. #1 12 13 14 15 16 17 18 19 20 21 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZi, j tWHQX #2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write 5 PARAMETER MIN 20 15 15 8 0 15 0 0 7 5 MAX MIN 25 20 20 10 0 20 0 0 10 5 MAX MIN 35 25 25 12 0 25 0 0 13 5 MAX MIN 45 30 30 15 0 30 0 0 15 MAX ns ns ns ns ns ns ns ns ns ns STK10C48-20 STK10C48-25
(VCC = 5.0V 10%)b
STK10C48-35 STK10C48-45 UNITS
Note j: If W is low when E goes low, the outputs remain in the high-impedance state. Note k: E or W must be VIH during address transitions. NE VIH.
SRAM WRITE CYCLE #1: W Controlledk
tAVAV ADDRESS tELWH E
14 19 12
tWHAX
tAVWH
18 tAVWL 13
17
W
tWLWH
15
tDVWH DATA IN tWLQZ DATA OUT
PREVIOUS DATA HIGH IMPEDANCE 20 DATA VALID
16 tWHDX
tWHQX
21
SRAM WRITE CYCLE #2: E Controlledk
tAVAV ADDRESS tAVEL E
18 14 19 12
tELEH
tEHAX
tAVEH W tWLEH
16 13
17
tDVEH DATA IN DATA OUT
HIGH IMPEDANCE DATA VALID
15
tEHDX
July 1999
3-4
STK10C48
MODE SELECTION
E H L L L L L L W X H L H L L H G X L X L H L H NE X H H L L L X MODE Not Selected Read SRAM Write SRAM Nonvolatile RECALL Nonvolatile STORE No Operation
l
POWER Standby Active Active Active ICC2 Active
Note l:
An automatic RECALL takes place at power up, starting when VCC exceeds 4.25V and taking tRESTORE.
STORE CYCLES #1 & #2
SYMBOLS NO. #1 22 23 24 25 26 27 28 tNLWL tELWL tWLEL tWLQXm tWLNHn #2 tELQX tELNH Alt. tSTORE tWC STORE Cycle Time STORE Initiation Cycle Time Output Disable Set-up to NE Fall tGHEL tNLEL Output Disable Set-up to E Fall NE Set-up Chip Enable Set-up Write Enable Set-up PARAMETER
(VCC = 5.0V 10%)b
MIN MAX 10 20 5 5 5 5 5 UNITS ms ns ns ns ns ns ns
tGHNL
Note m: Measured with W and NE both returned high, and G returned low. STORE cycles are inhibited below 4.0V. Note n: Once tWC has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W or E may be used to terminate the STORE initiation cycle. Note o: If E is low for any period of time in which W is high while G and NE are low, then a RECALL cycle may be initiated.
STORE CYCLE #1: W Controlledo
NE
G W
24 tGHNL
26 tNLWL
23 tWLNH
E
27 tELWL
HIGH IMPEDANCE
22 tWLQX
DQ (DATA OUT)
STORE CYCLE #2: E Controlledo
NE
26 tNLEL 25 tGHEL
G W E
28 tWLEL 23 tELNH
HIGH IMPEDANCE
22 tELQX
DQ (DATA OUT)
July 1999
3-5
STK10C48
RECALL CYCLES #1, #2 & #3
SYMBOLS NO. #1 29 30 31 32 33 34 35 36 tNLQXp tNLNH
q
(VCC = 5.0V 10%)b
PARAMETER MIN MAX 20 20 5 5 5 5 20 550 UNITS s ns ns ns ns ns ns s
#2 tELQX tELNH tNLEL
#3 tGLQX tGLNH tNLGL RECALL Cycle Time RECALL Initiation Cycle Time NE Set-up Output Enable Set-up tWHGL tELGL Write Enable Set-up Chip Enable Set-up NE Fall to Outputs Inactive Power-up RECALL Duration
tGLNL
tWHNL tELNL tNLQZ tRESTORE
tGLEL tWHEL tGLEL
Note p: Measured with W and NE both high, and G and E low. Note q: Once tNLNH has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to terminate the RECALL initiation cycle. Note r: If W is low at any point in which both E and NE are low and G is high, then a STORE cycle will be initiated instead of a RECALL.
RECALL CYCLE #1: NE Controlledo
NE
30 tNLNH 32 tGLNL
G
W
33 tWHNL 34 tELNL 29 tNLQX
HIGH IMPEDANCE
E
35 tNLQZ
DQ (DATA OUT)
RECALL CYCLE #2: E Controlledo
31 tNLEL
NE
32 tGLEL
G
W E
33 tWHEL
30 tELNH 29 tELQX
DQ (DATA OUT)
HIGH IMPEDANCE
RECALL CYCLE #3: G Controlledo, r
NE G
31 tNLGL 30 tGLNH
33 tWHGL 34 tELGL
W E
DQ (DATA OUT)
HIGH IMPEDANCE
29 tGLQX
July 1999
3-6
STK10C48
DEVICE OPERATION
The STK10C48 has two modes of operation: SRAM mode and nonvolatile mode, determined by the state of the NE pin. When in SRAM mode, the memory operates as a standard fast static RAM. While in nonvolatile mode, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM.
NONVOLATILE STORE
A STORE cycle is performed when NE, E and W and low and G is high. While any sequence that achieves this state will initiate a STORE, only W initiation (STORE cycle #1) and E initiation (STORE cycle #2) are practical without risking an unintentional SRAM WRITE that would disturb SRAM data. During a STORE cycle, previous nonvolatile data is erased and the SRAM contents are then programmed into nonvolatile elements. Once a STORE cycle is initiated, further input and output are disabled and the DQ0-7 pins are tri-stated until the cycle is complete. If E and G are low and W and NE are high at the end of the cycle, a READ will be performed and the outputs will go active, signaling the end of the STORE.
NOISE CONSIDERATIONS
Note that the STK10C48 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1F connected between VCC and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems.
SRAM READ
The STK10C48 performs a READ cycle whenever E and G are low and NE and W are high. The address specified on pins A0-10 determines which of the 2,048 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high or W or NE is brought low.
NONVOLATILE RECALL
A RECALL cycle is performed when E, G and NE are low and W is high. Like the STORE cycle, RECALL is initiated when the last of the four clock signals goes to the RECALL state. Once initiated, the RECALL cycle will take tNLQX to complete, during which all inputs are ignored. When the RECALL completes, any READ or WRITE state on the input pins will take effect. Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the nonvolatile cells. The nonvolatile data can be recalled an unlimited number of times. As with the STORE cycle, a transition must occur on any one control pin to cause a RECALL, preventing inadvertent multi-triggering. On power up, once VCC exceeds 4.25V, a RECALL cycle is automatically initiated. Due to this automatic RECALL, SRAM operation cannot commence until tRESTORE after VCC exceeds 4.25V.
SRAM WRITE
A WRITE cycle is performed whenever E and W are low and NE is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low.
POWER-UP RECALL
During power up, or after any low-power condition (VCC < 3.0V), an internal RECALL request will be latched. When VCC once again exceeds 4.25V, a RECALL cycle will automatically be initiated and will take tRESTORE to complete.
July 1999
3-7
STK10C48
If the STK10C48 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected either between W and system VCC or between E and system VCC.
LOW AVERAGE ACTIVE POWER
The STK10C48 draws significantly less current when it is cycled at times longer than 55ns. Figure 2 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK10C48 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the VCC level; and 7) I/ O loading.
HARDWARE PROTECT
The STK10C48 offers two levels of protection to suppress inadvertent STORE cycles. If the control signals (E, G, W and NE) remain in the STORE condition at the end of a STORE cycle, a second STORE cycle will not be started. The STORE (or RECALL) will be initiated only after a transition on any one of these signals to the required state. In addition to multi-trigger protection, STOREs are inhibited when VCC is below 4.0V, protecting against inadvertent STOREs.
100
100
Average Active Current (mA)
80
Average Active Current (mA)
80
60
60 TTL CMOS 20
40 TTL 20 CMOS 0 50 100 150 Cycle Time (ns) 200
40
0 50 100 150 Cycle Time (ns) 200
Figure 2: ICC (max) Reads
Figure 3: ICC (max) Writes
July 1999
3-8
STK10C48 ORDERING INFORMATION
STK10C48 - P 25 I Temperature Range
Blank = Commercial (0 to 70C) I = Industrial (-40 to 85C)
Access Time
20 = 20ns (Commercial only) 25 = 25ns 35 = 35ns 45 = 45ns
Package
P = Plastic 28-pin 300 mil DIP N = Plastic 28-pin 300 mil SOIC S = Plastic 28-pin 350 mil SOIC
July 1999
3-9

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